`timescale 1ns/1ps
`default_nettype none

module pixel_display_buf (
    // write
    input  wire         I_wclk,
    input  wire [7:0]   I_wren,
    input  wire [7:0]   I_waddr,
    input  wire [35:0]  I_wdata,
    // read
    input  wire         I_rclk,
    input  wire         I_rden,
    input  wire [9:0]   I_raddr,
    output wire [71:0]  O_rdata
);
//------------------------Parameter----------------------

//------------------------Local signal-------------------

//------------------------Instantiation------------------
genvar i;
generate
    for (i = 0; i < 8; i= i + 1) begin : gen_ram
        // sdpram_256x36_1024x9
        sdpram_256x36_1024x9 ram (
            .data      ( I_wdata ),
            .rdaddress ( I_raddr ),
            .rdclock   ( I_rclk ),
            .rden      ( I_rden ),
            .wraddress ( I_waddr ),
            .wrclock   ( I_wclk ),
            .wren      ( I_wren[i] ),
            .q         ( O_rdata[i*9+8:i*9] )
        );
    end
endgenerate

//------------------------Body---------------------------

endmodule

`default_nettype wire

// vim:set ts=4 sw=4 et fenc=utf-8 fdm=marker:
